1. Field of the Invention
The invention relates to an integrated selection circuit for four potentials, namely that of the zero point of the circuit (U0) and three potentials U1, U2, U3 differing therefrom, and which is realized in a complementary insulated-gate field-effect transistor technology, hence the so-called CMOS technology.
2. Description of the Invention
In certain cases of practical application of the CMOS technology, the problem arises of connecting potentials as low ohmic as possible to predetermined circuit parts of a voluminous circuit system. One such case of practical application, for example, exists with the subject matter of the simultaneously filed European Patent Application entitled "Integrated circuit for the writing, reading and erasing of storage matrices with the aid of insulated-gate field effect transistors having a non-volatile storage behaviour" having the European filing number 81102460.3, which will be also further filed in the United States of America. In this case of practical application, the potentials to be connected through are intended to serve the programming of the transistors having a non-volatile storage behaviour. The invention, however, is in no way restricted to this particular case of practical application, but may be used in all cases where a CMOS circuit is required for the selection of a maximum of four potentials, and with the internal resistance thereof, as seen from the output, being supposed to be as low-ohmic as possible.